A semiconductor memory device has been continuously improved in its integrated degree and its operation speed. For rising the operating speed, so called, a synchronous memory device is introduced, which operates in synchronous with a clock from external of a memory chip.
The first suggested one is so called a SDR (Single Data Rate) synchronous memory device, which inputs or outputs one data over one clock cycle at a data pin in synchronous with a rising edge of the clock from the external of the memory device.
However, the SDR synchronous memory device is also short to satisfy system speed for high-speed operation. Therefore, a DDR (Double Data Rate) synchronous memory device is introduced, which processes two data for one clock cycle.
In the DDR synchronous memory device, two data are subsequently inputted or outputted at its data input or output pins in synchronous with the rising edge and the falling edge of the clock form the external of the memory device. As such, the DDR synchronous memory device gets to implement the high-speed operation because its bandwidth gets to at least two times than the conventional SDR synchronous memory device, without increasing the frequency of the clock.
However, because the DDR memory device should output or input two data for one clock cycle, in order to perform these data input and output effectively, the data access scheme that is used in the conventional synchronous memory device cannot be used for the DDR memory device.
Providing 10 nsec as the clock cycle and considering time for rising and falling (0.5×4=2 nsec) and time for other specification, two data should be processed substantially within about 6 nsec. Because the memory device is short to perform such a processing within itself, the memory device inputs or outputs data at the rising edge and the falling edge of the clock only for inputting or outputting data to/from the outside of the memory device, and substantially parallel processes two data synchronized to one edge of the clock within the memory device.
Accordingly, a new data access scheme is requested to transfer data from the memory device to an inner core region or output data from the inner core region to external.
For this purpose, a data input buffer of the DDR memory device pre-fetches 2-bit data that are synchronized to the rising edge and the falling edge and then transfers those data to the inner core region by synchronizing them to a rising edge of a main clock as even data or odd data.
However, as a semiconductor device such as a CPU(Central Processing Unit) increases its speed, the memory device is requested to operate at a higher speed. For this, there has been suggested a data input buffer that pre-fetches 4-bit data to transfer to the internal of the memory device.
On the other hand, to implement accurate timing for data input or output, when the memory device receives the data, a data strobe signal(hereinafter, a DQS signal) is inputted in addition to the data signal from the CPU or a memory controller which is located at the external of the memory device.
FIG. 1 is a block diagram for a 4-bit data pre-fetch data input buffer of a synchronous memory device according to the conventional technique.
Referring to FIG. 1, the buffer includes a data buffering unit 10 for buffering inputted data, a data align latching unit 20 for latching and aligning the input data to a first and a second rising data or a first and a second falling data, a multiplexer 30 for receiving the aligned 4 data align_dr0, align_df0, align_dr1, aling_df1 to selectively output them as odd data OD0, OD1 and even data EV0, EV1, a gio(global input/output) line driver 40 for transferring the odd data OD0, OD1 and the even data EV0, EV1 in response to an internal strove signal data_strobe to a globtal input/output line, and a data strobe buffering unit 50 for outputting a rising pulse dsrp and a falling pulse dsfp, each being generated at the rising edge and the falling edge of the DQS signal, by being enabled by an enable signal en_din that is generated by a write command.
FIG. 2 is a block diagram for the data align latching unit 20 shown in FIG. 1.
Referring to FIG. 2, the data align latching unit 20 includes a first rising latching unit 21 for latching data outputted from the data buffering unit 10 with the rising pulse dsrp to output as a first rising data rising_d0, a second rising latching unit 22 for latching the first rising data rising_d0 with the falling pulse dsfp to output a third align data align_dr1, a third rising latching unit 140 for latching the third align data align_dr1 with the rising pulse dsrp to output a second rising data rising_d1, a fourth rising latching unit 26 for latching the second rising data rising_d1 with the falling pulse dsfp to output a first align data align_r0, a first falling latching unit 23 for latching the data outputted from the data buffering unit 10 with the falling pulse dsfp to output a fourth align data align_df1, a second falling latching unit 25 for latching the fourth align data align_df1 with the rising pulse dsrp to output a falling data falling_d1, and a third falling latching 27 for latching the falling data falling_d1 with the falling pulse dsfp to output a second align data align_df0.
FIG. 3 is a block diagram for the data strobe buffering unit 50 shown in FIG. 1.
Referring to FIG. 1, the data strobe buffering unit 50 includes NMOS transistors MN1, MN2 for receiving a reference signal Vref and a DQS signal through their gates, respectively, an NMOS transistor MN3 for receiving an enable signal en_din, that is generated by a write command, at its gate, one end of the NMOS transistor MN3 being commonly coupled to one end of each of the NMOS transistors MN1, MN2 and the other end being connected to the ground voltage VSS, a PMOS transistor MP1 for connecting a power voltage VDD to the other end of the NMOS transistor MN1, the gate of the PMOS transistor MP1 being diode-coupled to the other end of the NMOS transistor MN1, a PMOS transistor MP2 for connecting the power voltage VDD to the other end of the NMOS transistor MN2 for forming a current mirror with the PMOS transistor MP1, a PMOS transistor MP3 for receiving the enable signal en_din at its gate and connecting the power voltage VDD to the other end of the NMOS transistor MN1, a PMOS transistor MP4 receiving the inverted version of the enable signal en_din at its gate and connecting the power voltage VDD to the other end of the NMOS transistor MN2, serially coupled inverters I1, I2, I3 for buffering and outputting the common node of the PMOS transistor MP2 and the NMOS transistor MN2, inverters I7, I8 serially coupled to the inverter I3 for outputting the rising pulse, and inverters I4, I5, I6 serially coupled to the inverter I3 for outputting the falling pulse.
FIG. 4 is a waveform diagram for illustrating the operation when BL=8 in the synchronous memory device shown in FIG. 1. It will be described for the operation of the memory device with reference to FIGS. 1 to 4.
First, data D0-D7 are inputted in synchronous with the rising edge and the falling edge of the operation clock CLK and a DQS signal is inputted at the timing when the data D0-D7 are inputted.
The data strobe buffering unit 50 is enabled by the enable signal en_din that is generated by the write command to generate the rising pulse dsrp that is outputted as a pulse at the rising edge of the DQS signal and the falling pulse dsfp that is outputted as a pulse at the falling edge of the DQS signal.
While sustaining high impedance state when there is no operation, the DQS signal is clocked according to the timing when the data are inputted in a preamble state (X period in FIG. 4) in which the DQS signal goes to and keeps low level one clock earlier than the data is inputted. Upon receiving all the data, the DQS signal stays in a post-amble state (Y period in FIG. 4) of the low level for a while and then returns to and keeps the high impedance state.
In turn, the first rising latching unit 21 latches the first, the third, the fifth and the seventh data D0, D2, D4, D6 at the rising pulse dsrp to output as the first rising data rising_d0.
In turn, the second rising latching unit 22 latches the first rising data rising_d0 at the falling pulse dsfp to output the third align data align_r1, and the first falling latching unit 23 latches the second, the fourth, the sixth and the eighth data D1, D3, D5, D7 at the falling pulse dsfp to output as the fourth align data align_f1.
In turn, the third rising latching unit 24 latches the third align data align_r1 at the rising pulse dsrp to output as the second rising data rising_d1 and the second falling latching unit 25 latches the fourth align data align_f1 at the rising pulse dsrp to output the falling data falling_d1.
In turn, the fourth rising latching unit 26 latches the second rising data rising_d1 at the falling pulse dsfp to output the first align data align_r0, and the third falling latching unit 27 latches the falling data align_df0 at the falling pulse fsfp4 to output the second align data align_f0.
In turn, the multiplexer 30 receives the first to the fourth align data align_dr0, align_df0, align_dr1, align_df1 to output the even data EV0, EV1 and the odd data OD0, OD1. Here, the select signal that is inputted to the multiplexer 30 is to select the multiplexer at a mode when the memory device gets 4 data or 8 data simultaneously.
In turn, the gio line driver 40 transfers the even data EV0, EV1 or the odd data OD0, OD1 to the global input/output line in response to the inner strobe signal data_strobe. After that, data that is transferred to the global input/output line is transferred to a cell array.
FIG. 5 is a waveform diagram for explaining the shortage of the memory device shown in FIG. 1. It will be described for the shortage of the conventional memory device with reference to FIGS. 1 to 5.
As described above, while sustaining high impedance state when there is no operation, the DQS signal is clocked while the data is inputted in synchronous with the rising pulse and the falling pulse of the operation clock CLK, and returns to the high impedance state after input of all the data.
However, during return to the high impedance state after input of all the data, ripple happens, which is to cause error because of overshoot of the ripple.
That is, due to the overshoot during return of the data strobe signal to the high impedance, the inverters I4-I8 happen to operate to generate a dummy rising pulse and a dummy falling pulse (see, X in FIG. 5) even after input of all the data so as to probably damage the latched data.